Prior microprocessors often employ circuitry for performing a built-in self test ("BIST") of internal circuit blocks. During a BIST sequence, a plurality of test patterns are delivered to internal circuit blocks and the responses of the circuit blocks are then observed. Thus test pattern generation and response observation are two primary functions performed by BIST circuitry.
The internal circuitry of a microprocessor is often separated into combinational blocks and sequential blocks, the sequential blocks comprising clocked circuitry such as flip-flops. One prior circuit used for testing combinational and sequential circuit blocks in a microprocessor is a "scan chain." A scan chain includes a plurality of storage elements that are cascaded such that the output of a first storage element is coupled to the input of the next stage storage element. Scan chains thus allow a user of the microprocessor to test circuit blocks by serially scanning in test patterns to the storage elements. The test patterns are then applied to the circuit block, and circuit test results are serially scanned out. The use of these scan chains can be costly because test patterns must be stored and applied by an external tester. Moreover, scan chains are slow because the circuit responses must be scanned out and compared by the tester subsequent to the application of each test pattern.
One advantage of incorporating BIST capability in to a microprocessor is that required test patterns are self-generated by the BIST circuitry. The test patterns may either be generated prior to the BIST sequence and stored in internal memory, or the test pattern generation may occur as the BIST sequence is being performed. The latter method is advantageous in that it eliminates a need for potentially large storage areas in which test patterns must be held.
The BIST circuitry is not only used for test pattern generation, but is also used for circuit response observation. One response observation method involves comparing the result of each circuit response with its corresponding expected pattern. This method is burdensome, especially for complex circuit blocks with large numbers of outputs, because the large volumes of patterns must be compared. Another method of response observation is called response compression, wherein the output of the response is passed through a compactor that will generate a compressed output, called a signature. The signature, being of smaller size than the circuit output response, can then be compared with its corresponding expected signature value.
FIG. 1 illustrates a block diagram of a prior art BIST circuit including a circular path 170. The circular path 170 is capable of acting as a cyclic shift register, wherein the output of each flip-flop is shifted in to the input of the next stage, with the output of the last flip-flop 113 being fed back to the input of flip-flop 110. The FIG. 1 embodiment is often referred to as Circular BIST ("CBIST").
The CBIST circuit of FIG. 1 is capable of performing both pattern generation and signature generation simultaneously. The multiplexers 120a-d are used to select the input to the flip-flops 110-113. The input selected can either be the output of the circuit block 100, or the shift input, which is the output of the previous stage XOR gate. When the shift input is selected, the XOR gates 130a-d facilitate pattern generation and signature compression within the circular path 170. The operation of the CBIST circuit shown in FIG. 1 is discussed in: Krasniewski and Pilarski, Circular Self-Test Path: A Low-Cost BIST Technique, ACM/IEEE Design Automation Conference Proceedings, 1987.
Although the CBIST scheme of FIG. 1 allows for simultaneous pattern generation and compression, one problem with CBIST is that the test patterns generated are dependent upon the circuit block 100. This limits fault coverage of the circuit block 100 by limiting the richness of the test patterns generated. The CBIST implementation of FIG. 1 also has a large circuit delay and area penalty due to the need for one XOR gate and multiplexer per flip-flop.
FIG. 2 illustrates another prior BIST circuit known as a primitive polynomial linear feedback shift register (LFSR). The LFSR of FIG. 2 can be used for both test pattern generation and signature generation. The LFSR comprises a chain of scan flip-flops 210-213, each scan flip-flop having the functionality of a flip-flop and a 2-input multiplexer. This allows each flip-flop to receive one of two inputs, a shift input from the previous stage flip-flop or the outputs 230a-d from a circuit block (not shown).
The LFSR is first initialized with a data string, known as the test seed. The LFSR is then shifted, wherein the feedback path 250 and XOR gate 240 of the LFSR create a new data pattern in the flip-flops 210-213. The new data pattern is predictable; the LFSR will generate a pattern in accordance with a characteristic polynomial. The LFSR of FIG. 2 is constructed such that the characteristic polynomial is a "primitive polynomial." Primitive polynomial LFSRs will generate a maximum-length test sequence, thus increasing the fault coverage for a circuit block above that for a non-primitive LFSR. The BIST patterns generated by an LFSR are therefore less dependent on the circuit block than the CBIST scheme shown in FIG. 1. Because the output test patterns of an LFSR appear to be almost random, the test patterns are termed "pseudo-random" sequences.
A problem with LFSRs, however, is that its XOR feedback paths take up a lot of circuit area within the microprocessor. This is especially a problem for LFSRs comprised of many flip-flops, used for testing circuit blocks with large numbers of inputs and outputs. Another problem associated with LFSRs is that it takes a long time for LFSRs to sequence through all of the test patterns. Moreover, LFSRs can only be used to test combinational logic circuits, limiting their applicability for testing the internal circuitry of a microprocessor.
One prior art technique of minimizing test times while still providing good circuit fault coverage involves "reseeding" of an LFSR. Reseeding occurs when the LFSR is interrupted and provided with a new test seed before the completion of a test sequence. This technique is believed to provide high fault coverage of the circuit block while reducing the time required for test sequences to complete. An explanation of this reseeding hypothesis is located in: Pomeranz and Reddy, A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test, International Test Conference Proceedings (IEEE Computer Society, 1993). A problem with one implementation of this reseeding scheme is that it involves a large amount of circuit area. Memory is required to store the potentially large number of test seeds, and additional circuitry is needed to retrieve each new test seed from memory and load the seed into the LFSR.
Both the CBIST circuit of FIG. 1 and the LFSR circuit of FIG. 2 require a significant amount of circuit area and produce a significant time delay during testing. The LFSR reseeding technique improves testing times, but requires a large amount of circuit area for test seed storage. It is therefore desirable to incorporate a BIST circuit within a microprocessor that decreases circuit area and delay times while maximizing circuit fault coverage.